1. Field of the Invention
The present invention relates to a charge pumping circuit. More particularly, the invention relates to a charge pumping circuit insensitive to change in the threshold voltage of a transistor, and a direct current converting apparatus using the same.
2. Discussion of Related Technology
A conventional charge pumping circuit is configured to output a voltage with a higher level than the voltage supplied from a power source. Charge pumping circuits can be employed as a back-bias voltage generator of a semiconductor device, such as a dynamic random access memory (DRAM), and a voltage generator for generating voltage for writing and erasing programs in the cells of an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory device.
FIG. 1 is a circuit diagram illustrating an exemplary charge pumping circuit 10. Referring to FIG. 1, the charge pumping circuit 10 includes a source transistor MS and a voltage pumping unit 12. The source transistor MS is connected to an input terminal Vin, supplying an input voltage Vdd, to operate as a diode so that the source transistor MS supplies the input voltage Vdd to the voltage pumping unit 12.
The voltage pumping unit 12 comprises first through fourth transmission transistors M1-M4 and first through fourth capacitors C1-C4. The first to fourth transmission transistors M1-M4 are connected to the output port of the source transistor MS in a series configuration. In the exemplary circuit 10, the source transistor MS and the first to fourth transmission transistors M1-M4 are n-type metal-oxide semiconductor field effect transistors (NMOSFET).
The first electrode of the first capacitor C1 is connected to a first node N1 between the source transistor MS and the first transmission transistor M1. The second electrode of the first capacitor C1 is connected to a first clock signal line CL1 to which a first clock signal CLK1 is supplied.
The first electrode of the second capacitor C2 is connected to a second node N2 between the first transmission transistor M1 and the second transmission transistor M2. The second electrode of the second capacitor C2 is connected to a second clock signal line CL2 to which a second clock signal CLK2 is supplied.
The first electrode of the third capacitor C3 is connected to a third node N3 between the second transmission transistor M2 and the third transmission transistor M3. The second electrode of the third capacitor C3 is connected to the first clock signal line CL1 to which the first clock signal CLK1 is supplied.
The first electrode of the fourth capacitor C4 is connected to a fourth node N4 between the third transmission transistor M3 and the fourth transmission transistor M4. The second electrode of the fourth capacitor C4 is connected to the second clock signal line CL2 to which the second clock signal CLK2 is supplied.
The first clock signal CLK1 supplied to the first clock signal line CL1 and the second clock signal CLK2 supplied to the second clock signal line CL2 are two-phase clock signals having a phase difference of 18020 .
The gate electrodes of the series connected first to fourth transmission transistors M1-M4 are connected to the source electrodes thereof to operate as diodes. More particularly, the gate electrode of the first transmission transistor M1 is connected to the first node N1, the gate electrode of the second transmission transistor M2 is connected to the second node N2, the gate electrode of the third transmission transistor M3 is connected to the third node N3, and the gate electrode of the fourth transmission transistor M4 is connected to the fourth node N4.
The voltage pumping unit 12 is configured to pump the input voltage Vdd output from the source transistor MS in stages using the first to fourth transmission transistors M1-M4, in accordance with the first and second clock signals CLK1 and CLK2, to output the pumped voltage to the final output terminal Vout.
Thereby, the input voltage Vdd supplied to the charge pumping circuit 10 has a higher level at the final output terminal Vout due to an increase in pumping time, which is generated by the first and second clock signals CLK1 and CLK2.
The input voltage Vdd is charged at the first node N1 of the charge pumping circuit 10 through the source transistor MS, which is connected to the input terminal Vin to operate as a diode. Therefore, the voltage at the first node is related to the input voltage Vdd according to Equation 1, wherein, VN1, Vth, and VCLK1 represent the voltage at the first node N1, the threshold voltage of the source transistor MS, and the voltage of the first clock signal CLK1.VN1=Vdd−Vth+VCLK1   (1)
Because the charge pumping circuit 10 is sensitive to the threshold voltage Vth of the source transistor MS, which may be too high in relation to the input voltage for the source transistor MS to operate optimally, pumping efficiency deteriorates.